1. Field of the Invention
The present invention generally relates to the field of semiconductor component manufacturing. More specifically, the present invention relates to the simultaneous manufacturing in a semiconductor substrate, of capacitors, low-voltage transistors and high-voltage transistors, for example, for EEPROM-type memory devices.
2. Discussion of the Related Art
FIGS. 1 to 4 schematically illustrate in cross-section successive steps of a conventional manufacturing method of different semiconductor components on the same substrate.
As illustrated in FIG. 1, a lightly-doped substrate 1 of a first conductivity type (hereafter, type P) in which active areas have been defined between field oxide areas 2 is considered. A first mask 3 is deposited and etched to only expose the areas through which capacitors are to be formed. Then, through the openings of this first mask 3, an N-type dopant is implanted at low energy to create a first electrode 4 of a capacitor.
As illustrated in FIG. 2, after removing the first mask 3, a second mask 5 is deposited and opened to only expose the areas in which low-voltage P-channel transistors are to be formed. Then, a high energy N-type backward implantation is performed through the openings of this second mask 5 to create wells 6 of low voltage P-channel transistors. This implantation crosses the thick oxide and may be followed by another N-type implantation. Conversely to what has been shown, mask region 5 is not necessarily provided above the insulating areas between P-channel transistors. The wells 6 of these P-channel transistors may thus be contiguous.
As illustrated in FIG. 3, after removing second mask 5, a third mask 7 is deposited and opened, to only expose the areas in which the low voltage N-channel transistors are to be formed. Then, a high energy P-type backward implantation is performed through the openings of this third mask 7, to create wells 8 of low voltage N-channel transistors. This implantation crosses the thick oxide.
At the next steps, illustrated in FIG. 4, third mask 7 is removed, a fourth mask 9 is deposited and opened, to only protect the areas in which N-type wells 6 of the low voltage P-channel transistors have been formed. In the embodiment shown, field oxide areas 2 separating two low voltage P-channel transistors are exposed. Then, a high energy P-type backward implantation is performed through the openings of this fourth mask 9, to form heavily-doped regions 10. This implantation crosses the thick oxide. Implantation 10 is formed under the capacitor layers 4, in complement in areas 8 of the low voltage N-channel transistors, as well as in areas of the high voltage N-channel transistors. Further, implantation 10, if desired, avoids creating a parasitic channel between the N-type wells of two adjacent low voltage P-channel transistors.
Thus, to form the wells of low voltage N- and P-channel transistors, a capacitor electrode area, and stop-channel regions, a conventional method requires four successive masking and implantation-diffusion steps.